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W42C27
Specialty Clock Generator
Features
* Supports 3.3V and 5V operation * W42C27-36 provides the same functionality but stronger output drive than the W42C27-13 (obsolete) * Proprietary crystal oscillator circuitry provides low REF jitter, excellent duty cycle * Integral PLL loop filter components ensure stable PLL operation in noisy system environments * Output clocks are TTL or CMOS-level compatible * Custom options available with metal layer changes * Low power CMOS design available in: -- 8-pin SOIC (Small Outline Integrated Circuit) Table 1. Input/Output Frequency Selection W42C27-41 FS1 0 0 1 1 FS0 0 1 0 1 Reference (input) 17.734 17.734 14.318 14.318 CLK 48.625 96.059 48.682 96.016 Ratio (P/Q) 85/31 65/12 17/5 114/17
Table 2. Product Selection Guide Part -36 -41 Input (MHz) 17 14.318 Output (MHz) 106.25 Selectable Application Fibre Channel Digital Cameras
Functional Block Diagram: W42C27 Base Feature Set
STOPCPU SLOWCPU FS0 FS1 FS2 FS3 Frequency Selection ROM
/P - PFD + Loop Filter MUX /Q Crystal Oscillator OUT B Latched Gate
VCO
/d
/2
OUT A
/2
OUT C OE
Pin Configurations
W42C27-36
AGND GND X1 X2 1 2 3 4 8 7 6 5 106.25MHz AVDD VDD OE FS0 GND X1 X2
W42C27-41
1 2 3 4
8 7 6 5
FS1 REF VDD CLK
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 September 28, 1999, rev. **
W42C27
Pin Definitions
Pin Name 106.25MHz AGND AVDD CLK FS0:1 GND OE REF VDD X1 X2 Pin Type O G P O I G I O P I I Pin Description 106.25-MHz reference clock for FC-AL chipsets Analog ground connection Analog Power Connection Clock output (refer to Table 1 on page 1) Frequency Selection inputs[1] Ground connection Output Enable, puts clock outputs in high-impedance state when LOW[1] Reference Clock output, outputs crystal or input clock frequency Power supply connection Crystal connection or external clock frequency input[1] Crystal connection, leave this pin unconnected when using external clock
Note: 1. All inputs, except X1/X2 have an internal pull-up resistor. Unconnected inputs will assume a logic HIGH condition.
Overview
The W42C27 is a general-purpose device that features a single phase-locked loop. Through the use of metal masks, the chip can be tailored to a wide variety of applications. The W42C27 can have up to three output frequencies. A wide variety of input functions are available through mask options. W42C27-36 Option Description The standard W42C27-36 option provides a fixed 106.25-MHz clock output that is useful in FC-AL (Fiber Channel Arbitrated Loop) applications. FC-AL chip sets, such as the Vitesse VSC7105/7106, require a 106.25-MHz input reference clock. Unlike other Cypress clock products, the W42C27-36 requires a 17.0-MHz crystal or reference clock source. To maintain the 106.25-MHz 50 ppm accuracy required by FC-AL applications, the 17.0-MHz crystal needs to be controlled to within 50 ppm (the 106.25-MHz output is derived by the PLL ratio of 25/4 x 17.0 MHz). To facilitate precise frequency control of the crystal oscillator, external crystal load capacitors are used and required with the W42C27-36 option; no internal load capacitors
are implemented at device pin X1 and X2 (again unlike other Cypress clock devices). The required load capacitance value for accurate crystal oscillation frequency is specified by the crystal manufacturer. Stray capacitance of X1 and X2 is about 5 pF. Improved Crystal Oscillator Circuit The W42C27 incorporates a new crystal oscillator circuit designed to provide 50% duty cycle over a range of operating conditions including the addition of external crystal load capacitors to pins X1 and X2. (Crystal load capacitance is sometimes increased to match a particular crystal load requirement when absolute frequency accuracy is important.) Duty cycle is also maintained when using an external clock source (connected to pin X1, pin X2 is left open), as long as the external clock has good duty cycle. Crystal load capacitance of the W42C27 is about 10 pF (excluding the W42C27-36 option), which is becoming an industry standard. This helps to control frequency accuracy, assuming that a crystal which specifies a 10-pF load condition is used. The circuit exhibits about 50% less clock jitter from the REF output when compared to similar devices.
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W42C27
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions Parameter VDD, VIN TSTG TA TB Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 Unit V C C C
Electrical Characteristics at 5.0V DC Electrical Characteristics: TA = 0C to +70C; VDD = 5V 10%
Parameter IDD VIL VIH VOL VOH VOH CI CL IIL IIH RP Description Operating Supply Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage Input Capacitance Load Capacitance Input Low Current Input High Current Input Pull-Up Resistor IOL = 8 mA IOH = -0.1 mA IOH = -4 mA Except X1, X2 Pins X1, X2 (except for -36) VIN = 0V (includes pull-up resistor) VIN = VDD VIN = 0V 250 10 -100 10 VDD - 0.4V 2.4 10 2.0 0.4 Note 2 Conditions Min Typ Max 25 0.8 Unit mA V V V V V pF pF A A k
AC Characteristics: TA = 0C to +70C; VDD = 5V 10%
Parameter FO FI TR TR TF TF DT TJ1S TJABS TPU Output Frequency Input Frequency Output Rise Time, 0.8 to 2.0V, 25-pF Load Output Rise Time, 20 to 80% V CC, 25-pF Load Output Fall Time, 2.0 to 0.8V, 25-pF Load Output Fall Time, 80 to 20% VCC, 25-pF Load Duty Cycle, 15-pF Load Jitter, 1 Sigma, All Frequencies Jitter, Absolute, All Frequencies Powerup Time, Off to stated output frequency 15 40 Description Min 2 2 14.318 1 2 1 2 50 Typ Max 120 32 2 4 2 4 60 150 250 30 Unit MHz MHz ns ns ns ns % ps ps ms
Note: 2. W42C27 with no load. Power supply current varies with frequency.
3
W42C27
Electrical Characteristics at 3.3V DC Electrical Characteristics: TA = 0C to +70C; VDD = 3.3V 5%
Parameter IDD VIL VIH VOL VOH CI CL IIL IIH RP Description Operating Supply Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Capacitance Load Capacitance Input Low Current Input High Current Input Pull-Up Resistor IOL = 8 mA IOH = -4 mA Except X1, X2 Pins X1, X2 VIN = 0V (includes pull-up resistor) VIN = V DD VIN = 0V 250 10 -100 10 2.4 10 2.0 0.4 Note 2 Conditions Min Typ Max 20 0.8 Unit mA V V V V pF pF A A k
AC Characteristics: TA = 0C to +70C; VDD = 3.3V 5%
Parameter FO FI ICLKR ICLKF TR TF DT TJ1S TJABS TPU Output Frequency Input Frequency Input Clock Rise Time Input Clock Fall Time Output Rise Time, 20 to 80% V CC, 25-pF Load Output Fall Time, 80 to 20% VCC, 25-pF Load Duty Cycle, 15-pF Load Jitter, 1 Sigma, All Frequencies Jitter, Absolute, All Frequencies Powerup Time, Off to stated output frequency 15 40 2 2 50 Description Min 2 2 14.318 Typ Max 110 32 20 20 4 4 60 150 250 30 Unit MHz MHz ns ns ns ns % ps ps ms
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W42C27
Recommended Circuit Configuration
VDD Optional Ferrite Bead 2.2 F
AGND GND
AVDD 0.1 F VDD 0.1 F
Recommended Circuit Configuration
For optimum performance in system applications, the above power supply decoupling scheme should be used. GND pins are connected directly to the ground plane. VDD decoupling is important to reduce phase jitter and EMI radiation. The 0.1-F decoupling capacitor should be placed as close to the VDD pins as possible, otherwise the increased trace inductance will negate its decoupling capability. The 2.2-F decoupling capacitor shown is optional but will improve
power supply rejection. For further EMI protection, the VDD connection can be made via a ferrite bead, as shown. When using the W42C27, unused input select pins may be tied to either ground or V DD, or may be left unconnected. Since internal pull-up resistors are incorporated on all logic input pins, an unconnected input will assume a logic 1 condition. Output clocks should use a series termination resistor (about 33) placed as close to the clock outputs as possible; this will also help to decrease jitter, EMI and clock signal ringing.
Ordering Information
Ordering Code W42C27 Document #: 38-00804 Freq. Mask Code 36, 41 Package Name G Package Type 8-pin SOIC (150-mil)
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W42C27
Package Diagrams
8-Pin Small Outline Integrated Circuit, Narrow (SOIC, 0.150 inch)
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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